1999 Mar 09

27

Philips Semiconductors

Product specification

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

Notes to the characteristics

1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST

frequency). Conversion-to-noise ratio: S/N = EB

× 6.02 + 1.76 dB.

available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then

be rechecked.

400 kbit/s (400 kHz).

start condition hold time

4.0

−−

µs

start condition set-up time

repeated start

4.7

−−

µs

LOW level clock period

4.7

−−

µs

HIGH level clock period

4.0

−−

µs

data set-up time

250

−−

ns

data hold time

0

−−

ns

SDA and SCL rise time

−−

1.0

µs

SDA and SCL fall time

−−

300

ns

stop condition set-up time

4.0

−−

µs

capacitive load for each bus

line

−−

400

pF

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Fig.11 Timing diagram.

handbook, full pagewidth

td(s)

sample N

+ 1

sample N

CKADCO

n

MGL103

sample N

+ 2

50 % = 1.4 V

1.4 V

2.4 V

0.4 V

VlN

DATA

R0 to R7, ROR

G0 to G7, GOR

B0 to B7, BOR

td(o)

th(o)

tCPH

tCPL

In + 2

In + 1

In

In − 1