DS28EC20 datasheet(21/24 Pages) DALLAS

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DS28EC20: 20Kb 1-Wire EEPROM

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Slave-to-Master

A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the

read low time tRL is expired. During the tRL window, when responding with a 0, the DS28EC20 starts pulling the data

line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When

responding with a 1, the DS28EC20 does not hold the data line low at all, and the voltage starts rising as soon as

tRL is over.

The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS28EC20 on the other side

define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line.

For the most reliable communication, tRL should be as short as permissible, and the master should read close to

but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This

guarantees sufficient recovery time tREC for the DS28EC20 to get ready for the next time slot. Note that tREC

specified herein applies only to a single DS28EC20 attached to a 1-Wire line. For multidevice configurations, tREC

needs to be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface

that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line

drivers can be used.

IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)

In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire

driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and

topology of the network, reflections from end points and branch points can add up or cancel each other to some

extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the

1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can

cause a slave device to lose synchronization with the master and, consequently, result in a Search ROM command

coming to a dead end or cause a device-specific function command to abort. For better performance in network

applications, the DS28EC20 uses a new 1-Wire front-end, which makes it less sensitive to noise.

The 1-Wire front-end of the DS28EC20 differs from traditional slave devices in three characteristics:

1) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.

This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at overdrive speed.

2) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but does not go

below VTH - VHY, it is not recognized (Figure 12, Case A). The hysteresis is effective at any 1-Wire speed.

3) There is a time window specified by the rising edge hold-off time tREH during which glitches are ignored, even if

they extend below VTH - VHY threshold (Figure 12, Case B, tGL < tREH). Deep voltage droops or glitches that

appear late after crossing the VTH threshold and extend beyond the tREH window cannot be filtered out and are

taken as the beginning of a new time slot (Figure 12, Case C, tGL ≥ tREH).

Devices that have the parameters VHY and tREH specified in their electrical characteristics use the improved 1-Wire

front-end.

Figure 12. Noise Suppression Scheme

VPUP

VTH

VHY

tREH

tGL

tREH

tGL

Case A

Case C

Case B

DS28EC20 Datasheet(PDF) 21 Page - Dallas Semiconductor

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