TUSB8020BPHPR datasheet(11/44 Pages) TI

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TUSB8020B

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SLLSEF6C – JULY 2014 – REVISED JUNE 2017

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8.3.4 Clock Generation

The TUSB8020B accepts a crystal input to drive an internal oscillator or an external clock source. If a crystal is

used, a 1-M

Ω shunt resistor is required. Keep the XI and XO traces as short as possible and away from any

switching leads to minimize noise coupling.

Figure 2. TUSB8020B Clock

8.3.4.1 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 to 24 pF and frequency stability rating of

±100 PPM or better. To ensure proper startup oscillation condition, TI recommends a maximum crystal

equivalent series resistance (ESR) of 50 Ω. A parallel load capacitor should be used if a crystal source is used.

The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and

Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122) for details on how to determine the

load capacitance value.

8.3.4.2 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or

better frequency stability and have less than 50-ps absolute peak-to-peak jitter or less than 25-ps peak-to-peak

jitter after applying the USB 3.0 jitter transfer function. XI should be tied to the 1.8-V clock source and XO should

be left floating.

8.3.5 Power-Up and Reset

The TUSB8020B does not have specific power sequencing requirements with respect to the VDD or VDD33

power rails. The VDD or VDD33 power rails may be powered up for an indefinite period of time while the other is

not powered up if all of these constraints are met:

•

All maximum ratings and recommended operating conditions are observed.

•

All warnings about exposure to maximum rated and recommended conditions are observed, particularly

junction temperature. These apply to power transitions as well as normal operation.

•

Bus contention while VDD33 is powered-up must be limited to 100 hours over the projected lifetime of the

device.

•

Bus contention while VDD33 is powered-down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. A supply bus is

powered down when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required, which is defined as the time when the power supplies are in the

recommended operating range to the deassertion of GRSTz. This can be generated using programmable-delay

supervisory device or using an RC circuit.

TUSB8020BPHPR Datasheet(PDF) 11 Page - Texas Instruments

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