CS4360

22

DS517F2

*Requires MCLKDIV bit = 1 in the Mode Control 2 register (address 0Ch)

4.3

Digital Interface Format

The device will accept audio samples in 1 of 4 digital interface formats in Stand-alone mode, as illustrated

in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 8.

4.3.1

Stand-Alone Mode

The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship

between the LRCK, SCLK and SDIN, see Figures 15-17.

Sample Rate

(kHz)

MCLK (MHz)

64x

96x

128x

192x

256x*

176.4

11.2896

16.9344

22.5792

33.8688

45.1584

192

12.2880

18.4320

24.5760

36.8640

49.1520

Table 5. Quad-speed Mode Standard Frequencies

DIF1

DIF0

DESCRIPTION

FORMAT

FIGURE

00

Left Justified, up to 24-bit Data

016

01

115

10

Right Justified, 16-bit Data

217

11

Right Justified, 24-bit Data

317

Table 6. Digital Interface Format - Stand-alone Mode