CS5101A datasheet(16/39 Pages) CIRRUS

16 / 39 page

CS5101A CS5102A

DS45F6

3.1

Calibration

The ability of the CS5101A or the CS5102A to con-

vert accurately to 16-bits clearly depends on the

accuracy of its comparator and DAC. Each device

utilizes an “auto-zeroing” scheme to null errors in-

troduced by the comparator. All offsets are stored

on the capacitor array while in the track mode and

are effectively subtracted from the input signal

when a conversion is initiated. Auto-zeroing en-

hances power supply rejection at frequencies well

below the conversion rate.

To achieve 16-bit accuracy from the DAC, the

CS5101A and CS5102A use a novel self-calibra-

tion scheme. Each bit capacitor shown in Figure 3

actually consists of several capacitors in parallel

which can be manipulated to adjust the overall bit

weight. An on-chip microcontroller precisely ad-

justs each capacitor with a resolution of 18 bits.

The CS5101A and CS5102A should be reset upon

power-up, thus initiating a calibration cycle. The

device then stores its calibration coefficients in on-

chip SRAM. When the CS5101A and CS5102A are

in power-down mode (SLEEP low), they retain the

calibration coefficients in memory, and need not be

recalibrated when normal operation is resumed.

CS5101A Datasheet(PDF) 16 Page - Cirrus Logic