UMA1015MSLASHC2 datasheet(4/24 Pages) PHILIPS

4 / 24 page

1995 Jun 22

Philips Semiconductors

Product speciﬁcation

Low-power dual frequency synthesizer

for radio communications

UMA1015M

PINNING

SYMBOL

DESCRIPTION

output Port 1

output Port 2

CPA

charge-pump output synthesizer A

VDD1

digital supply voltage 1

HPD

hardware power-down

(input LOW = power-down)

RFA

RF input synthesizer A

DGND

digital ground

fXTALIN

common crystal frequency input from

TCXO

output Port 3

fXTALO

open-drain output of fXTAL signal

CLK

programming bus clock input

DATA

programming bus data input

programming bus enable input

(active LOW)

VDD2

digital supply voltage 2

RFB

RF input synthesizer B

AGND

analog ground to charge pumps

CPB

charge pump output synthesizer B

VCC

analog supply to charge pump;

external or voltage doubler output

P0/OOL

Port output 0/out-of-lock output

ISET

regulator pin to set charge-pump

currents

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

Main dividers

Each synthesizer has a fully programmable 17-bit main

divider. The RF input drives a pre-amplifier to provide the

clock to the first divider bit. The pre-amplifier has a high

input impedance, dominated by pin and pad capacitance.

The circuit operates with signal levels from below

50 mV (RMS) up to 250 mV (RMS), and at frequencies up

to 1.1 GHz. The high frequency sections of the divider are

implemented using bipolar transistors, while the slower

section uses CMOS technology. The range of division

ratios is 512 to 131071.

Reference divider

There is a common fully programmable 12-bit reference

divider for the two synthesizers. The input fXTALIN drives a

pre-amplifier to provide the clock input for the reference

divider. This clock signal is also buffered and output on pin

fXTALO (open drain). An extra divide-by-2 block allows a

reference comparison frequency for synthesizer B to be

half that of synthesizer A. This feature is selectable using

the program bit SR. If the programmed reference divider

ratio is R then the ratio for each synthesizer is as given in

Table 1.

The range for the division ratio R is 8 to 4095. Opposite

edges of the divider output are used to drive the phase

detectors to ensure that active edges arrive at the phase

detectors of each synthesizer at different times. This

minimizes the potential for interference between the

charge pumps of each loop. The reference divider consists

of CMOS devices operating beyond 35 MHz.

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