1995 Jun 22

7

Philips Semiconductors

Product specification

Low-power dual frequency synthesizer

for radio communications

UMA1015M

Power-down modes

The device can be powered down either via pin HPD

(active LOW = power-down) or via the serial bus (bits

SPDA and SPDB, logic 0 = power-down). The

synthesizers are powered up when both hardware and

software Power-down signals are at logic 1. When only

one synthesizer is powered down, the functions common

to both will be maintained. When both synthesizers are

switched off, only the voltage doubler (if enabled) will

remain active drawing a reduced current. An internal

oscillator will drive the doubler in this situation. If both

synthesizers have been in a power-down condition, then

when one or both synthesizers are reactivated, the

reference and main dividers restart in such a way as to

avoid large random phase errors at the phase comparator.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling MOS devices.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

DC range of digital power supply voltage with respect

to DGND

−0.3

+6.0

V

DC charge pump supply voltage with respect to AGND

−0.3

+6.0

V

∆V

CC-DD

−0.3

+6.0

V

DC voltage at pins 1, 2, 5, 6, 8 to 15, 19 and 20 with

respect to DGND

−0.3

V

DC voltage at pins 3 and 17 with respect to AGND

−0.3

V

∆V

GND

difference in voltage between AGND and DGND

(these pins should be connected together)

−0.3

+0.3

V

storage temperature

−55

+125

°C

operating ambient temperature

−30

+85

°C