Table 2

Bit allocation

Note

1. The test register should not be programmed with any other values except all zeros for normal operation.

FIRST

REGISTER BIT ALLOCATION

LAST

p1

p2

p3

p4

p5

p6

p7

p8

p9

p10

p11

p12

p13

p14

p15

p16

p17

p18

p19

p20

p21

dt16

dt15 dt14

dt13 dt12

DATA FIELD

dt4

dt3

dt2

dt1

dt0

ADDRESS

X

X

VDON PO

OLA

OLB

CRA

CRB

X

X

sPDA sPDB P3

P2

P1

X

X

0

0

0

1

MA16

SYNTHESIZER A MAIN DIVIDER COEFFICIENT

MA0

0

1

0

0

0

0

0

0

SR

R11

REFERENCE DIVIDER COEFFICIENT

R0

0

1

0

1

MB16

SYNTHESIZER B MAIN DIVIDER COEFFICIENT

MB0

0

1

1

0

0000

Table 3

Bit allocation description

Table 4

Out-of-lock select

SYMBOL

DESCRIPTION

sPDA, sPDB

software power-down for synthesizers A and B (0 = power-down)

P3, P2, P1 and P0

bits output to pins 1, 2, 9 and 19 (1 = high impedance)

VDON

voltage doubler enable (1 = doubler enabled)

OLA, OLB

out-of-lock select; selects signal output to pin 19 (see Table 4)

CRA, CRB

SR

reference frequency ratio select (see Table 6)

OLA

OLB

OUTPUT AT PIN 19

00

P0

0

1

lock status of loop B; OOLB

1

0

lock status of loop A; OOLA

1

1

logic OR function of loops A and B

Table 5

Charge pump current ratio

CRA/CRB

CURRENT AT PUMP

Table 6

Reference division ratio

SR

SYNTHESIZER A

SYNTHESIZER B

0R

R

1R

2R