M69KB128AA datasheet(21/68 Pages) STMICROELECTRONICS

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M69KB128AA

6 Synchronous operating modes

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6.4

Synchronous Burst Read Interrupt

Ongoing Burst Read operations can be interrupted to start a new Burst cycle by either of the

following means:

●

Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended). If

necessary, refresh cycles will be added during the new Burst operation to schedule any

outstanding refresh. If Variable Latency mode is set, additional wait cycles will be added if

a refresh operation is scheduled during the Synchronous Burst Read Interrupt. WAIT

monitoring is mandatory for proper system operation.

●

Starting a new Synchronous Burst Read operation without toggling E.

An ongoing Burst Read operation can be interrupted only after the first valid data is output.

When a new Burst access starts, I/O signals immediately become high impedance.

6.5

Synchronous Burst Write Interrupt

Ongoing Burst Write operations can be interrupted to start a new Burst cycle by either of the

following means:

●

Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended),

●

Starting a new Synchronous Burst Write without toggling E. Considering that Burst Writes

are always performed in Fixed Latency mode, refresh is never scheduled. A maximum

Chip Enable, E, low time (tELEH) must be respected for proper device operation.

An ongoing Burst Write can be interrupted only after the first data is input. When a new Burst

access starts, I/O signals immediately become high impedance.

See Figure 27: Burst Read Interrupted by Burst Read or Write AC Waveforms and Figure 32:

Burst Write Interrupted by Burst Write or Read AC Waveforms for details on Burst Read and

Burst Write interrupt AC waveforms, respectively.

6.6

Synchronous Burst Read and Write Suspend

Synchronous Burst Read and Write operations can be suspended by halting the Clock K

holding it either High or Low. The status of the I/O signals will depend on the status of Output

enable input, G. The device internal address counter is suspended and data outputs become

high impedance tGHQZ after the rising edge of the Output Enable signal, G. It is prohibited to

suspend the first data output at the beginning of a Synchronous Burst Read.

See Figure 25 for details on the Synchronous Burst Read and Write Suspend mechanisms.

During Synchronous Burst Read and Synchronous Burst Write Suspend operations, the WAIT

output will be asserted. Bit BCR8 of the Bus Configuration Register is used to configure when

the transition of the WAIT output signal between the asserted and the deasserted state occurs

with respect to valid data available on the data bus.

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