M69KB128AA datasheet(30/68 Pages) STMICROELECTRONICS

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7 Configuration registers

M69KB128AA

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7.3

Bus Configuration Register

The Bus Configuration Register (BCR) defines how the PSRAM interacts with the system

memory bus. All the device operating modes are configured through the BCR, except the Page

mode which is configured through the RCR.

Refer to Table 9 for the description of the Bus Configuration Register Bits.

7.3.1

Operating Mode Bit (BCR15)

The Operating Mode bit allows the Synchronous mode or the Asynchronous mode (default

setting) to be selected. Selecting the Synchronous mode will allow the device to operate either

in NOR Flash mode or in full Synchronous Burst mode.

The device will automatically detect that the NOR Flash mode is being used by monitoring a

rising edge of the Clock signal, K, when L is Low. If this should not be the case, the device

operates in full Synchronous mode.

7.3.2

Latency Type (BCR14)

The Latency Type bit is used to configure the latency type. When the Latency Type bit is set to

‘0’, the device operates in variable latency mode (only available for Synchronous Read mode).

When it is ‘1’, the fixed latency mode is selected and the latency is defined by the values of bits

BCR13 to BCR11.

Refer to Table 3 and Table 4 for examples of fixed and variable latency configuration.

7.3.3

Latency Counter Bits (BCR13-BCR11)

The Latency Counter bits are used to set the number of clock cycles between the beginning of

a read or write operation and the first data output or input.

The Latency Counter bits can only assume the values shown in Table 9: Bus Configuration

7.3.4

WAIT Polarity Bit (BCR10)

The WAIT Polarity bit indicates whether the WAIT output signal is active High or Low. As a

consequence, it also determines whether the WAIT signal requires a pull-up or pull-down

resistor to maintain the de-asserted state (see Figure 10: WAIT Polarity).

By default, the WAIT output signal is active High.

7.3.5

WAIT Configuration Bit (BCR8)

The system memory microcontroller uses the WAIT signal to control data transfer during

Synchronous Burst Read and Write operations.

The WAIT Configuration bit is used to determine when the transition of the WAIT output signal

between the asserted and the deasserted state occurs with respect to valid data available on

the data bus. When the Wait Configuration bit is set to ‘0’, data is valid or invalid on the first

Clock rising edge immediately after the WAIT signal transition to the deasserted or asserted

state. When the Wait Configuration bit is set to ‘1’ (default settings), the WAIT signal transition

occurs one clock cycle prior to the data bus going valid or invalid.

See Figure 9: WAIT Configuration Example for an example of WAIT configuration.

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