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M69KB128AA Datasheet(PDF) 26 Page - STMicroelectronics |
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M69KB128AA Datasheet(HTML) 26 Page - STMicroelectronics |
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26 / 68 page ![]() 6 Synchronous operating modes M69KB128AA 26/68 Figure 5. Switching from Asynchronous to Synchronous Write operation Figure 6. Refresh Collision during Synchronous Read Operation in Variable Latency mode 1. Additional Wait states are inserted to allow Refresh completion. The latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT must be active Low, VIL, (BCR10 = 0) and asserted during delay (BCR8= 0). Addr. K AI10203 E W L VALID tAVWL tELKH A0-A22 WAIT DQ0-DQ15 K Additional WAIT states inserted to allow Refresh completion Address Valid AI11275b L E G W Hi Z Hi Z LB/UB Q0 Q1 Q2 Q3 |
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