RTL8305SC
Datasheet
5-port 10/100Mbps Single-Chip Dual MII Switch Controller
9
Track ID: JATR-1076-21 Rev. 1.2
5.
Pin Descriptions
‘Type’ codes used in the following tables: A=Analog; D=Digital, I=Input; O=Output,
PU=Internal pull-up, PD=Internal pull-down.
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
5.1. Media Connection Pins
Table 2. Media Connection Pins
Pin Name
Pin No.
Type
Drive (mA) Description
RXIP[4:0]
RXIN[4:0]
2, 3, 12, 13,
16, 17, 26,
27, 30, 31
I
Differential Receive Data Input
Shared by 100Base-TX, 10Base-T, and 100Base-FX.
UTP or FX depends on pin GxMode/GyMode/P4Mode[1:0].
TXOP[4:0]
TXON[4:0]
5, 6, 9, 10,
19, 20, 23,
24, 33, 34
O
Differential Transmit Data Output
Shared by 100Base-TX, 10Base-T, and 100Base-FX.
UTP or FX depends on pin GxMode/GyMode/P4Mode[1:0].
5.2. Port 4 Configuration Pins
Table 3. Port 4 Configuration Pin Definitions
Pin Name
Pin No.
Type
Drive (mA) Description
Port 4 Configuration Pin Definitions
DISDUALMII
42
IPU
Disable Dual MII Interface Function
This pin disables or enables the Dual MII interface function of
port 4.
1: Disable
0: Enable
When enabled, the MAC circuit of port 4 can be set as MAC
mode MII, PHY mode MII, or PHY mode SNI. The PHY
circuit of port 4 is set as PHY mode MII.
The PHY circuit of port 4 can optionally be set as UTP or fiber
mode according to the P4MOD[1:0] configuration.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
