RTL8305SC
Datasheet
5-port 10/100Mbps Single-Chip Dual MII Switch Controller
27
Track ID: JATR-1076-21 Rev. 1.2
6.
EEPROM Description
6.1. Port 0 Registers
6.1.1.
Global Control Register0
Table 12. Global Control Register0
Name
Byte.bit Description
Default
EEPROM Existence
0.7
1: EEPROM does not exist (pin EnEEPROM=0 or pin EnEEPROM=1 but
EEPROM does not exist)
0: EEPROM exists (pin EnEEPROM=1 and EEPROM exists)
0
Reserved
0.6
1
Internal Use
0.5
1
Internal Use
0.4
1
Internal Use
0.3
1
Enable Loop
Detection Function
0.2
1: Enable loop detection function
0: Disable loop detection function
0
Reserved
0.1
1
Internal Use
0.0
0
6.1.2.
Global Control Register1
Table 13. Global Control Register1
Name
Byte.bit
Description
Default
Page selection
1.7
1: Select the registers in page 1
0: Select the registers in page 0
0
Reserved
1.6
0
Lookup table
accessible enable
1.5
1: Lookup table is accessible via indirect access registers
0: Lookup table is not accessible
0
Internal Use
1.4
0
Reserved
1.3
0
Disable 802.1Q
tag aware VLAN
1.2
1: Disable 802.1Q tagged-VID Aware function. The RTL8305SC will not
check the tagged VID on received frames to perform tagged-VID VLAN
mapping. Under this configuration, the RTL8305SC only uses the per port
VLAN index register to perform Port-Based VLAN mapping
0: Enable the Member Set Filtering function of VLAN Ingress Rule. The
RTL8305SC checks the tagged VID on received frames with the
VIDA[11:0]~VIDH[11:0] to index to a member set, then performs VLAN
mapping. The RTL8305SC uses tagged-VID VLAN mapping for tagged
frames but still uses Port-Based VLAN mapping for priority-tagged and
untagged frames
1
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