GS9215 datasheet(15/18 Pages) NIKOSEM

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Rev.:0P12 (Preliminary Specification)

Aug-12

GStek series

NIKO-SEM

GStek series

High Performance Single Synchronous

Buck Converter

GS9215

system applications.

Output Over Voltage Protection

When the output voltage rises up to 125% of the

preset voltage, the internal fault-logic module delays

about 20us and turns on the low side Power

MOSFET. It stays latched on and the GS9215 is

latched off until Power Reset or EN Reset.

Output Under Voltage Protection

When the output voltage falls down to 70% of the

preset voltage, the internal fault-logic module counts

256-CLKS and turns off both the high side and low

side Power MOSFETs. Both switches stay latched off

and the GS9215 is latched off until Power Reset or

EN Reset. During soft-start, the UVP will be blanked

around 512CLKS. But if the output voltage rises up

above the UVP threshold tolerance during the

counter period, the UVP counter is released

immediately.

UVLO and Soft-Start

An internal under voltage lockout (UVLO) module is

used to sense the VDD power supply. The PWM

controller is forbidden by the under voltage lockout

module when VDD rises above 4.3V, the GS9215 will

initial the control logic circuitries and soft-start

ramping generator, and then allows switching to

occur if both the device and VIN power Supply is

enabled. When VDD falls down to 3.9V, the PWM

controller is forbidden again. At this time, both sides

drive signal UGATE and LGATE are low.

After soft-start module starting, the GS9215

controller will limit the output current by 3-step

current limiting logic cycle by cycle over a

predetermined time period of 512CLKS. After UV

blanking time (512CLKS), the output under voltage

protection and power good indicator is enabled.

Power MOSFET Gate Drivers

The GS9215 has UGATE and LGATE drivers built-in,

which can drive two large external N-type MOSFET

used as high side and low side. External Boost diode

and capacitor are need to power the internal floating

drive module, A dead-time circuit is added to monitor

the UGATE output and to prevent the high-side

MOSFET from turning on until LGATE is fully off. The

internal pull-down transistor that drives LGATE low is

robust with a 0.5ohm typical on-resistance. The

instantaneous drive current is supplied by the flying

capacitor between VDDP and PGND. The dead-time

circuit also monitors the LGATE output and prevents

the low-side MOSFET from turning on until UGATE is

fully off. The typical dead time from UGATE-falling to

LGATE-rising is about 50ns.The typical dead time from

LGATE-falling to UGATE-rising is about 40ns.

External Devices Selection

For loop stability, the 0 dB frequency (f0), defined in the

follow equation:

RESR

OUT









The loop stability is determined by the output capacitor.

Specialty polymer capacitors have COUT in the order of

several 100uF and RESR in range of 10mohm is

recommended. However, ceramic capacitors have f0 at

more than 700 KHz, which is not recommended.

In order for the right regulate manner, the ripple voltage

at the feedback pin (FB), should be approximately

15mV. This generates Vripple= (VOUT/0.7) ×15mV at

the output node. The output capacitor RESR should

meet this equation.

The external device selection is list below:

Choose Feedback Voltage Divider Resistor

Set R5=1K~10K ohm

OUT







)

(

For output voltage Vout > 2.5V, Set VOUT PIN’s

voltage VOUT=2.5V.

Choose RVO2=1K~10K ohm

GS9215 Datasheet(PDF) 15 Page - NIKO SEMICONDUCTOR CO., LTD.

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