DEVICES INCORPORATED

LF3321

Horizontal Digital Image Filter

Improved Performance

LOGIC Devices Incorporated

1

Feb 5, 2003 LDS.3321-A

Video Imaging Products

111 MHz Data Rate

12-bit Data or Coefficients (Expandable to 24-bit)

32-Tap FIR Filter, Cascadable for More Filter Taps

LF Interface™ Allows All 256 Coefficient Sets to be

Updated Within Vertical Blanking

Over 49 K-bits of on-board Memory

Various Operating Modes: Dual Filter, Single Filter,

Double Wide Data or Coefficient, Matrix Multiplica-

tion, and Accumulator Access.

Selectable 16-bit Data Output with User-Defined

Rounding and Limiting

Supports Interleaved Data Streams

Supports Decimation up to 16:1 for Increas-

ing Number of Filter Taps

3.3 Volt Power Supply

144 Lead PQFP

The LF3321 is an improved version of the LF3320 Horizontal Digital Image Filter capable of operating at

speeds of up to 111MHz. This improved speed increases flexibility and performance and enables the user

to utilize this device in more applications. For example, four interleaved data streams of 27MHz can now

be processed within one device. The part is functionally identical to the LF3320 with the exception that the

filter data path is specified to operate faster than the LF Control Interface. When operating the filter at

speeds in excess of 90MHz, loading of coefficients via the LF Interface must be throttled to a maximum

of 90MHz by asserting the PAUSE pin as required to allow sufficient setup time for the configuration data

provided to the chip via the LF Interface.

Figure 1 demonstrates the switching waveforms, while the switching characteristics are given in Table

1. The LF3321 filters digital images in the horizontal dimension at real-time video rates. The input and

coefficient data are both 12 bits and in two’s complement format. The output is also in two’s complement

format and may be rounded to 16 bits.

The LF3321 is designed to take advantage of symmetric coefficient sets. When symmetric coefficient sets

are used, the device can be configured as a single 32-tap FIR filter or as two separate 16-tap FIR filters.

When asymmetric coefficient sets are used, the device can be configured as a single 16-tap FIR filter or as

two separate 8-tap FIR filters. Multiple LF3321s can be cascaded to create larger filters.

Interleave/Decimation Registers (I/D Registers) allow interleaved data to be fed directly into the device and

filtered without separating the data into individual data streams.

The LF3321 can handle a maximum of sixteen data sets interleaved together. The I/D Registers and

on-chip accumulators facilitate using decimation to increase the number of filter taps. Decimation of up

to 16:1 is supported.

allow all 256 coefficient sets to be updated within vertical blanking.

FEATURES

DESCRIPTION

tS0

tCFS

tPWH

tCYC

tPWL

ADDRESS

tPH

PAUSEA

PAUSEB

CFA 11-0

CFB 11-0

tLH

CLK

LDA

LDB

tCFH

tPS

CF0

CF1