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Issue 1.0.0

2017-12-05

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7

25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0

Fax: +49 (0) 4101 4058 19

e-mail: info@tews.com

www.tews.com

The Embedded I/O Company

TPMC533 32x ADC, 16x/0x DAC and 8x Digital I/O

Application Information

The TPMC533 is a standard single-wide PCI Mezzanine

Card (PMC) compatible module providing 32 channels of

simultaneous sampling true differential bipolar 16bit

analog input, 16 or no channels of simultaneous update

single-ended unipolar/bipolar 16bit analog output and 8

channels of tri-state 5V-tolerant TTL digital input/output.

All signals are accessible through a HDRA100 type front

I/O connector.

The PMC-Connectors P11 and P12 provide access to the

control logic via a 32bit 33MHz PCI interface.

The ADCs offer true differential inputs with software

selectable ±5V and ±10V bipolar input voltage ranges (one

common setting for all eight channels of each ADC). The

maximum sample rate of the ADCs is 200kSPS and they

offer an oversampling capability with digital filter.

The DACs offer software selectable 0-5V, 0-10V, 0-10.8V,

±5V, ±10V and ±10.8V output voltage ranges (individual

setting for each of the four channels of each DAC). The

settling time is typically 10μs and the DAC channels are

capable to drive a load of 2kΩ, with a capacitance up to

4000pF.

Each TPMC533 is factory calibrated. The correction data

is stored in an on-board serial EEPROM unique to each

PMC module. These correction values can be used to

perform a hardware correction of every analog-to-digital

and

digital-to-analog

conversion.

Additionally,

measurement data read out of a temperature sensor on-

board can be used to compensate temperature dependent

errors.

The TPMC533 provides two Sequencers, one for AD

Conversions and another one for DA Conversions. To

perform periodic simultaneous conversions the conversion

rates are programmable and can be output to other

modules on PMC Back I/O Connector P14 or Front I/O

Connector DIO pins for synchronization purposes. The

TPMC533 can also operate as a target which means that

the conversion rates can be sourced from P14 or Front

I/O, created by another module.

A Frame Trigger signal, which can also either be

generated by the TPMC533 and output on P14/Front I/O

or generated by other modules and input from P14/Front

I/O, can be used to synchronize ADC frames and DAC

frames.

The signals on PMC Back I/O Connector P14 are ESD

protected and driven or read by tri-state 5V-tolerant TTL

buffers.

To be able to collect ADC frames and to output DAC

frames the TPMC533 provides input and output FIFOs.

Data transfer on the PCI bus is handled by TPMC533

initiated block transfer mode DMA cycles with minimum

host/CPU intervention.