P89CV51RB2FBC datasheet(44/73 Pages) NXP

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P89CV51RB2_RC2_RD2_1

Product data sheet

Rev. 01 — 5 October 2007

44 of 73

NXP Semiconductors

P89CV51RB2/RC2/RD2

80C51 with 1 kB RAM, SPI

Table 33.

CMOD - PCA counter mode register (address C1H) bit description

Bit

Symbol

Description

CIDL

Counter Idle control. CIDL = 0 programs the PCA counter to continue

functioning during Idle mode; CIDL = 1 programs it to be gated off

during Idle mode.

WDTE

WatchDog Timer Enable. WDTE = 0 disables watchdog timer function

on module 4; WDTE = 1 enables it.

5 to 3

Reserved for future use. Should be set to 0 by user programs.

2 to 1

CPS1,

CPS0

PCA Count Pulse Select; see Table 34.

ECF

PCA Enable Counter overﬂow interrupt Flag. ECF = 1 enables CF bit

in CCON to generate an interrupt; ECF = 0 disables that function.

Table 34.

CMOD - PCA counter mode register (address C1H) count pulse select

CPS1

CPS0

Select PCA input

0 internal clock, fosc /6

1 internal clock, fosc /6

2 Timer 0 overﬂow

3 external clock at pin P1[2]/ECI (maximum rate = fosc /4)

Table 35.

CCON - PCA counter control register (address D8H) bit allocation

Bit addressable; reset value: 00H.

Bit

Symbol

CCF4

CCF3

CCF2

CCF1

CCF0

Table 36.

CCON - PCA counter control register (address D8H) bit description

Bit

Symbol

Description

PCA Counter overﬂow Flag. Set by hardware when the counter rolls

over. CF ﬂags an interrupt if bit ECF in CMOD is set. CF may be set by

either hardware or software but can only be cleared by software.

PCA Counter Run control. Set by software to turn the PCA counter on.

Must be cleared by software to turn the PCA counter off.

Reserved for future use. Should be set to 0 by user programs.

CCF4

PCA Module 4 interrupt Flag. Set by hardware when a match or