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WM8741 Datasheet(PDF) 24 Page - Wolfson Microelectronics plc |
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WM8741 Datasheet(HTML) 24 Page - Wolfson Microelectronics plc |
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24 / 63 page ![]() WM8741 Product Preview w PP Rev 1.3 October 2007 24 RIGHT JUSTIFIED MODE In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition. LRCLK is high during the left data word and low during the right data word. Figure 15 Right Justified Mode Timing Diagram I 2S MODE In I 2S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition. LRCLK is low during the left data word and high during the right data word. Figure 16 I2S Mode Timing Diagram |
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