SM5819AF

SEIKO NPC CORPORATION —7

DSD input

I

DSBCK pin

I

DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins

Note. DSD clock pulsewidth and DSD clock pulse cycle when DSBCK is in input mode.

Note. The data, with DSBCK timing above, enters the internal circuits on the falling edge of the MCK clock. Consequently, if the timing changes, the circuit

must be resynchronized using INIT or SYNC.

Parameter

Symbol

Rating

Unit

min

typ

max

DSD clock pulsewidth

150

177.16

–

ns

DSD clock pulse cycle

300

354.31 (1/64fs)

–

ns

DSD data setup time

50

–

–

ns

DSD data hold time

50

–

–

ns

DSI**: DSIFL, DSIFR, DSISL, DSISR, DSICT, DSISW pins

DSBCK

DSI**