TMPR4938 datasheet(47/716 Pages) TOSHIBA

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Chapter 1 Overview and Features

1-1

Overview and Features

1.1

Overview

The TMPR4938 (TX4938) is a standard microcontroller that belongs to the 64-bit TX System RISC TX49

family.

The TX4938 uses the TX49/H3 core as its CPU. The TX49/H3 core is a 64-bit RISC core that Toshiba

developed based on the MIPS III architecture of MIPS Technologies, Inc. (MIPS). For details of the

TX49/H3 core such as instruction sets, see “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core

Architecture”.

In addition to the TX49/H3 core, the TX4938 uses as microcontrollers for embedded applications an

External Bus Controller, DMA Controllers, SDRAM Controller, PCI Controller, Ethernet Controller and

NAND Flash Memory Controller (enables booting from NAND flash memory). The TX4938 also has

peripheral circuits such as a synchronous serial interface, on-chip SRAM, a serial I/O port, a timer/counter, a

parallel I/O port, an AC-link Controller and an Interrupt Controller. By having an on-chip a data bus with a

maximum width of 64 bits and an SDRAM Controller with a memory clock frequency of 133 MHz, the

TX4938 realizes low memory access latency and high memory bandwidth. This allows the TX4938 to show

its capacity as a high-performance CPU core.

1.2

Features

•

TX49/H3 core

Maximum Operating Frequency: 300 MHz (TMPR4938XBG-300), 333 MHz (TMPR4938XBG-333)

On-chip IEEE754-compliant single/double precision floating point unit (FPU) function

•

External Bus Controller (8 channels)

•

Supports the ISA/ATA interface

•

DMA (Direct Memory Access) Controllers (8 channels)

•

SDRAM Controller (4 channels)

64-bit Data Bus

Memory Clock Frequency: 133 MHz (For relationship between CPU clock and memory clock, see

Section 6.1)

Supports ECC/Parity

•

PCI Controller

Complies with PCI Local Bus Specification Revision 2.2

PCI Bus Clock Frequency: 66 MHz/33 MHz

•

Ethernet Controller (2 channels)

•

NAND Flash Memory Controller (bootable)

•

Serial Peripheral Interface (SPI)

•

On-chip SRAM (2 K-byte)

•

Serial I/O Port (2 channels)

•

Timer/Counter (3 channels)

•

Parallel I/O Port (Maximum 16 bits)

•

AC-link Controller

•

Interrupt Controller

•

Selectable Little Endian mode or Big Endian mode

TMPR4938 Datasheet(PDF) 47 Page - Toshiba Semiconductor

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