TMPR4938 datasheet(69/716 Pages) TOSHIBA

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Chapter 3 Signals

3-15

Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (2/2)

Signal

Description

Corresponding

Configuration

Determined at

ADDR[5]

Select SDRAM device

Select initial setting derivability of SDRAM interface signals

L = 8mA

H = 16mA

ADDR[19:0], CKE, RAS*, CAS*, WE*, SDCS[3:0], SDCLK[3:0],

SDCLKIN

PCFG[53:40]

RESET* deassert edge

ADDR[4]

Initial Setting of Boot

Select initial setting derivability of SDRAM interface signals

L = 8mA

H = 16mA

DATA[63:0], CB[7:0], DQM[7:0]

PCFG[56:54]

RESET* deassert edge

ADDR[3:0]

CPUCLK Clock Speed Setting

Specifies the value by which MASTERCLK input signal is multiplied

to produce the TX49/H3 core clock (CPUCLK).

The values of ADDR[1:0] are also reflected in the EC field of the

TX49/H3 core Config register.

ADDR[3:0] : DIVMODE[3:0]

HHHH:0100 CPUCLK frequency = 2 x MASTERCLK frequency

HHHL:1111 CPUCLK frequency = 2.5 x MASTERCLK frequency

HHLH:0101 CPUCLK frequency = 3 x MASTERCLK frequency

HHLL:0110 CPUCLK frequency = 4 x MASTERCLK frequency

LHHH:1101 CPUCLK frequency = 4.5 x MASTERCLK frequency

LHHL: -

reserved

LHLH: -

reserved

LHLL: -

reserved

HLHH:0000 CPUCLK frequency = 8 x MASTERCLK frequency

HLHL:1011 CPUCLK frequency = 10 x MASTERCLK frequency

HLLH:0001 CPUCLK frequency = 12 x MASTERCLK frequency

HLLL:0010 CPUCLK frequency = 16 x MASTERCLK frequency

LLHH:1001 CPUCLK frequency = 18 x MASTERCLK frequency

LLHL: -

reserved

LLLH: -

reserved

LLLL: -

reserved

CCFG.DIVMODE

CGRESET* deassert

edge

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