TMPR4938 datasheet(65/716 Pages) TOSHIBA

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Chapter 3 Signals

3-11

Table 3.1.16 Extended EJTAG Interface Signals (2/2)

Signal Name

Type

Description

Initial State

DCLK

Output

Debug Clock

Clock output signal for the real-time debugging system.

When PC trace mode is selected, the TPC[3:1] and PCST signals are output

synchronously. This clock is the TX49/H3 core operating clock (CPUCLK) divided by 3.

This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use

the configuration setting during boot-up.

Low

PCST[8:0]

Output

PC Trace Status Information

Outputs PC trace status and other information.

These signals are common with the other functions (refer to Section “3.3 Pin multiplex”).

Use the configuration setting during boot-up.

All Low

3.1.17 Clock Signals

Table 3.1.17 Clock Signals

Signal Name

Type

Description

Initial State

MASTERCLK

Input

Master Clock

Input pin for the TX4938 operating clock. A crystal resonator cannot be connected to this

pin because the pin does not contain an oscillator.

Input

HALTDOZE

Output

Halt/Doze State Output

This signal is asserted (High output) when the TX4938 enters Halt or Doze mode.

Low

BYPASSPLL*

Input

Bypass PLL

This pin must be fixed to High.

Input

CGRESET*

Input

CG Reset

CGRESET* initializes the CG.

Input

3.1.18 Initialization Signal

Table 3.1.18 Initialization Signal

Signal Name

Type

Description

Initial State

RESET*

Input

Reset

Reset signal.

Input

3.1.19 Test Signals

Table 3.1.19 Test Signals

Signal Name

Type

Description

Initial State

TEST[4:0]*

Input

Test Mode Setting

Test pins. These pins must be left open or fixed to High.

TEST[1]* may be used when debugging the system. Toshiba recommends that your

board design enable the pin to be driven low after the TX4938 is mounted on the PC

board. Contact Toshiba technical staff for more information on the TEST[1]* functions.

Input

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