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UPSD3422 Datasheet(PDF) 66 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 66 Page - STMicroelectronics |
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66 / 293 page ![]() Power saving modes uPSD34xx 66/293 Table 26. PCON: Power Control Register (SFR 87h, reset value 00h) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMOD0 SMOD1 – POR RCLK1 TCLK1 PD IDL Bit Symbol R/W Function 7 SMOD0 R,W Baud Rate Double Bit (UART0) 0 = No Doubling 1 = Doubling (See Section 21.3: UART baud rates on page 102 for details.) 6 SMOD1 R,W Baud Rate Double Bit for 2nd UART (UART1) 0 = No Doubling 1 = Doubling (See Section 21.3: UART baud rates on page 102 for details.) 5 – – Reserved 4POR R,W Only a power-on reset sets this bit (cold reset). Warm reset will not set this bit. 0 = Cleared to zero with firmware 1 = Is set only by a power-on reset generated by Supervisory circuit (see Section 19.3: Power-up reset on page 84 for details). 3 RCLK1 R,W Received Clock Flag (UART1) (See Table 43 on page 93 for flag description.) 2 TCLK1 R,W Transmit Clock Flag (UART1) (See Table 43 on page 93 for flag description) 1PD R,W Activate Power-down Mode 0 = Not in Power-down Mode 1 = Enter Power-down Mode 0 IDL R,W Activate Idle Mode 0 = Not in Idle Mode 1 = Enter Idle Mode |
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