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UPSD3422 Datasheet(PDF) 51 Page - STMicroelectronics |
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UPSD3422 Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 293 page ![]() uPSD34xx Debug unit 51/293 up to VCC as described in the section, Section 28.6.8: Debugging the 8032 MCU module on page 257. – The duration of a pulse, generated when the Event pin configured as an output, is one MCU clock cycle. This is an active-low signal, so the first edge when an event occurs is high-to-low. – The clock to the Watchdog Timer, ADC, and I2C interface are not stopped by a breakpoint halt. – The Watchdog Timer should be disabled while debugging with JTAG, else a reset will be generated upon a watchdog time-out. |
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