UPSD3422 datasheet(240/293 Pages) STMICROELECTRONICS

240 / 293 page

PSD module

uPSD34xx

240/293

28.5.50

Port D structure

Port D has two I/O pins (PD1, PD2) on 80-pin uPSD34xx devices, and just one pin (PD1) on

52-pin devices, supporting the following operating modes:

●

MCU I/O Mode

●

DPLD Output Mode for External Chip Selects, ECS1, ECS2. This does not consume

OMCs in the GPLD.

●

PLD Input Mode – direct input to the PLD Input Bus available to DPLD and GPLD. Does

not use IMCs

See Figure 88 on page 241 for detail.

Port D pins can also be configured in PSDsoft as pins for other dedicated functions:

●

PD1 can be used as a common clock input to all 16 OMC Flip-flops (see

Section 28.1.11: OMCs on page 189) and also the Section 28.5.52: Automatic power-

down (APD) on page 245.

●

PD2 can be used as a common chip select signal (CSI) for the Flash and SRAM

memories on the PSD Module (see Section 28.5.54: Chip select input (CSI) on

page 247). If driven to logic ’1’ by an external source, CSI will force all memories into

standby mode regardless of what other internal memory select signals are doing on the

PSD Module. This is specified in PSDsoft as “PSD Chip Select Input, CSI”.

Port D also supports the Fast Slew Rate output drive type option using the csiop Drive

Select registers.

UPSD3422 Datasheet(PDF) 240 Page - STMicroelectronics