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TMP86CS44UG Datasheet(PDF) 57 Page - Toshiba Semiconductor

Part # TMP86CS44UG
Description  8 Bit Microcontroller
PDF  172 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86CS44UG Datasheet(HTML) 57 Page - Toshiba Semiconductor

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Page 47
TMP86CS44UG
5. I/O Ports
The TMP86CS44UG has 5 parallel input/output ports (35 pins) as follows.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
input data should be externally held until the input data is read from outside or reading should be performed several
times before processing. Figure 5-1 shows input/output timing examples.
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction.
This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the
program.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
port.
Note: The positions of the read and write cycles may vary, depending on the instruction.
Figure 5-1 Input/Output Timing (Example)
Primary Function
Secondary Functions
Port P0
8-bit I/O port
External interrupt input, serial and timer/counter input/output
Port P1
8-bit I/O port
External interrupt input, timer/counter input/output, and divider output
Port P2
3-bit I/O port
External interrupt input, and STOP mode release signal input
Port P3
8-bit I/O port
Analog input, and STOP mode release signal input
Port P4
8-bit I/O port
Instruction
execution cycle
Input strobe
Data input
Ex: LD A, (x)
Fetch cycle
Fetch cycle
Read cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Instruction
execution cycle
Output strobe
Data output
Ex: LD (x), A
Fetch cycle
Fetch cycle
Write cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
(a) Input timing
(b) Output timing
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