TMP86CS44UG datasheet(132/172 Pages) TOSHIBA

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Page 122

11. Synchronous Serial Interface (SIO)

11.3 Function

TMP86CS44UG

Figure 11-14 Example of External Clock and MSB Transmit/Receive Mode

(4) Transmit/receive error processing

Transmit/receive errors occur on the following situation. Corrective action is different, which

errors occur transmits or receives.

(a) Transmit errors

Transmit errors occur on the following situation.

• Shift operation starts before writing next transmit data to SIOTDB in external clock op-

eration.

If transmit errors occur during transmit operation, SIOSR<TXERR> is set to “1” imme-

diately after starting shift operation. And INTSIO interrupt request is generated after all

of the 8-bit data has been received.

If shift operation starts before writing data to SIOTDB after SIOCR1<SIOS> is set to

“1”, SIOSR<TXERR> is set immediately after starting shift operation. And INTSIO in-

terrupt request is generated after all of the 8-bit data has been received.

SO pin is kept in high level when SIOSR<TXERR> is set to “1”. When transmit error

occurs, transmit operation must be forcibly stop by writing SIOCR1<SIOINH> to “1”

after the received data is read from SIORDB. In this case, SIOCR1<SIOS>, SIOSR reg-

ister, SIORDB register and SIOTDB register are initialized.

Writing transmit

data C

Writing transmit

data B

Writing transmit

data A

A7 A6

A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0

D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0

Start shift

operation

Start shift

operation

Start shift

operation

Clearing SIOS

Reading received data

Reading received

data F

Reading received

data E

Reading received

data D

Writing transmit data

SIOCR1<SIOS>

SIOSR<SIOF>

SIOSR<SEF>

SCK

pin output

SO pin

SI pin

INTSIO

interrupt

request

SIOSR<TXF>

SIOSR<RXF>

SIORDB

SIOTDB

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