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TMP86CS44UG Datasheet(PDF) 147 Page - Toshiba Semiconductor |
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TMP86CS44UG Datasheet(HTML) 147 Page - Toshiba Semiconductor |
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147 / 172 page  Page 137 TMP86CS44UG Note 1: Always set bit0 in ADCCR2 to "0" and set bit4 in ADCCR2 to "1". Note 2: When a read instruction for ADCCR2, bit6 to 7 in ADCCR2 read in as undefined data. Note 3: After STOP or SLOW/SLEEP mode are started, AD converter control register2 (ADCCR2) is all initialized and no data can be written in this register. Therfore, to use AD converter again, set the ADCCR2 newly after returning to NORMAL1 or NORMAL2 mode. Note 1: Setting for " −" in the above table are inhibited. fc: High Frequency oscillation clock [Hz] Note 2: Set conversion time setting should be kept more than the following time by Power supply voltage(VDD) . AD Converter Control Register 2 ADCCR2 (001DH) 7654 3210 IREFON "1" ACK "0" (Initial value: **0* 000*) IREFON DA converter (Ladder resistor) connection control 0: 1: Connected only during AD conversion Always connected R/W ACK AD conversion time select (Refer to the following table about the con- version time) 000: 001: 010: 011: 100: 101: 110: 111: 39/fc Reserved 78/fc 156/fc 312/fc 624/fc 1248/fc Reserved Table 13-1 ACK setting and Conversion time Condition Conversion time 16 MHz 8 MHz 4 MHz 2 MHz 10 MHz 5 MHz 2.5 MHz ACK 000 39/fc - - - 19.5 μs - - 15.6 μs 001 Reserved 010 78/fc - - 19.5 μs 39.0 μs - 15.6 μs 31.2 μs 011 156/fc - 19.5 μs 39.0 μs 78.0 μs 15.6 μs 31.2 μs 62.4 μs 100 312/fc 19.5 μs39.0 μs 78.0 μs 156.0 μs 31.2 μs 62.4 μs124.8 μs 101 624/fc 39.0 μs78.0 μs 156.0 μs - 62.4 μs124.8 μs- 110 1248/fc 78.0 μs 156.0 μs - - 124.8 μs- - 111 Reserved - VDD = 4.5 to 5.5 V 15.6 μs and more - VDD = 2.7 to 5.5 V 31.2 μs and more AD Converted value Register 1 ADCDR1 (001FH) 76543 210 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 (Initial value: 0000 0000) AD Converted value Register 2 ADCDR2 (001EH) 76543 210 AD01 AD00 EOCF ADBF (Initial value: 0000 ****) |
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