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TMP86CS44UG Datasheet(PDF) 165 Page - Toshiba Semiconductor |
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TMP86CS44UG Datasheet(HTML) 165 Page - Toshiba Semiconductor |
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165 / 172 page ![]() Page 155 TMP86CS44UG 17.5 DA Conversion Characteristics Note 1: In linearity error measurements, the first code (00H, 01H) and the last code (FEH, FFH) are excluded. Note 2: DA converter power consumption Note 3: DAO current drive capability (VSS = 0 V, VDD = 4.5 to 5.5 V, Topr = −40 to 85°C) Parameter Symbol Condition Min Typ. Max Unit Analog reference voltage AVDD AVDD = VDD 4.5 – 5.5 V AVSS AVSS = VSS VSS – VSS Resolution ––8 Bits Linearity error (Note1) AVDD = VDD = 4.5 to 5.5 V AVSS = VSS = 0 V Load conditions 5 pF, 10 M Ω –– ±5LSB Settling time 4ms Reference current (DA power consumption) (Note2) IDREF No load, VDD = 5.5 V, fc = 16 MHz – 350 500 μA DAO output current (Note3) IDAO AVDD = VDD = 4.5 V AVSS = VSS = 0 V No load 0.5 V bias when inputting 7FH 14 19 – (VSS = 0 V, VDD = 2.7 to 4.5 V, Topr = −40 to 85°C) Parameter Symbol Condition Min Typ. Max Unit Analog reference voltage AVDD AVDD = VDD 2.7 – 4.5 V AVSS AVSS = VSS VSS – VSS Resolution ––8 Bits Linearity error (Note1) AVDD = VDD = 2.7 to 4.5 V AVSS = VSS = 0 V Load conditions 5 pF, 10 M Ω −10°C ≤ Ta ≤ 85°C –– +5 LSB −8 −40°C ≤ Ta < −10°C –– +5 −26 Settling time 6ms Reference current (DA power consumption) (Note2) IDREF No load, VDD = 2.7 V, fc = 8 MHz – 200 300 μA DAO output current (Note3) IDAO AVDD = VDD = 2.7 V AVSS = VSS = 0 V No load 0.5 V bias when inputting 7FH 0.4 5.3 – |
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