TMP86CS64AFG datasheet(173/202 Pages) TOSHIBA

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TMP86CS64AFG

When an external clock is used, the data must be written to the data buffer register before shifting next data.

Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request

to writing of the data to the data buffer register by the interrupt service program.

The transmission is ended by clearing SIO2CR1<SIOS> to “0” or setting SIO2CR1<SIOINH> to “1” in

buffer empty interrupt service program.

SIO2CR1<SIOS> is cleared, the operation will end after all bits of words are transmitted.

That the transmission has ended can be determined from the status of SIO2SR<SIOF> because

SIO2SR<SIOF> is cleared to “0” when a transfer is completed.

When SIO2CR1<SIOINH> is set, the transmission is immediately ended and SIO2SR<SIOF> is cleared to

“0”.

When an external clock is used, it is also necessary to clear SIO2CR1<SIOS> to “0” before shifting the next

data; If SIO2CR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will

end.

If it is necessary to change the number of words, SIO2CR1<SIOS> should be cleared to “0”, then

SIO2CR2<BUF> must be rewritten after confirming that SIO2SR<SIOF> has been cleared to “0”.

Figure 16-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock)

DBR

Clear SIOS

Write

(a)

Write

(b)

SCK2 pin

(Output)

SO2 pin

INTSIO2 interrupt

SIO2CR1<SIOS>

SIO2SR<SIOF>

SIO2SR<SEF>

TMP86CS64AFG Datasheet(PDF) 173 Page - Toshiba Semiconductor