TMP86CS64AFG datasheet(171/202 Pages) TOSHIBA

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Page 161

TMP86CS64AFG

Figure 16-4 External clock pulse width

16.3.2 Shift edge

The leading edge is used to transmit, and the trailing edge is used to receive.

16.3.2.1 Leading edge

Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK2 pin input/

output).

16.3.2.2 Trailing edge

Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK2 pin input/out-

put).

Figure 16-5 Shift edge

16.4 Number of bits to transfer

Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of

the transmit/receive data buffer register are used. The upper 4 bits are cleared to “0” when receiving.

The data is transferred in sequence starting at the least significant bit (LSB).

16.5 Number of words to transfer

Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be trans-

ferred continuously. The number of words to be transferred can be selected by SIO2CR2<BUF>.

tSCKL tSCKH

tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes)

4/fs (In the SLOW1/2, SLEEP1/2 modes)

tSCKL, tSCKH > 4tcyc

SCK2

pin (Output)

Bit 1

Bit 2

Bit 3

*321

3210

**32

***3

Bit 0

Shift register

Bit 1

Bit 0

Bit 2

Bit 3

0***

****

210*

10**

3210

(a) Leading edge

(b) Trailing edge

*; Don’t care

SO2 pin

SI2 pin

SCK2 pin

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