AM79C961AVC datasheet(71/206 Pages) AMD

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Am79C961A

including the destination address, source address,

length/type and packet data.

The receive section of the MAC engine will detect an

incoming preamble sequence and lock to the encoded

clock. The internal MENDEC will decode the serial bit

stream and present this to the MAC engine. The MAC

will discard the first 8 bits of information before search-

ing for the SFD sequence. Once the SFD is detected,

all subsequent bits are treated as part of the frame. The

MAC engine will inspect the length field to ensure min-

imum frame size, strip unnecessary pad characters (if

enabled), and pass the remaining bytes through the

Receive FIFO to the host. If pad stripping is performed,

the MAC engine will also strip the received FCS bytes,

although the normal FCS computation and checking

will occur. Note that apart from pad stripping, the frame

will be passed unmodified to the host. If the length field

has a value of 46 or greater, the MAC engine will not

attempt to validate the length against the number of

bytes contained in the message.

If the frame terminates or suffers a collision before

64 bytes of infor mation (after SFD) have been

received, the MAC engine will automatically delete the

fr am e fr om t he Re ce iv e F I F O, with out h o s t

intervention.

Addressing (source and destination address

handling)

The first 6 bytes of information after SFD will be inter-

preted as the destination address field. The MAC

engine provides facilities for physical, logical, and

broadcast address reception. In addition, multiple

physical addresses can be constructed (perfect

address filtering) using external logic in conjunction

with the EADI interface.

Error detection (physical medium transmission

errors)

The MAC engine provides several facilities which

report and recover from errors on the medium. In addi-

tion, the network is protected from gross errors due to

inability of the host to keep pace with the MAC engine

activity.

On completion of transmission, the following transmit

status is available in the appropriate TMD and CSR

areas:

s The exact number of transmission retry attempts

(ONE, MORE, or RTRY).

s Whether the MAC engine had to Defer (DEF) due to

channel activity.

s Loss of Carrier, indicating that there was an inter-

ruption in the ability of the MAC engine to monitor its

own transmission. Repeated LCAR errors indicate

a pot e n t i ally fa ult y t ransceiver o r n e t wor k

connection.

s Late Collision (LCOL) indicates that the transmis-

sion suffered a collision after the slot time. This is

indicative of a badly configured network. Late colli-

sions should not occur in a normal operating net-

work.

s Collision Error (CERR) indicates that the trans-

ceiver did not respond with an SQE Test message

within the predetermined time after a transmission

completed. This may be due to a failed transceiver,

disconnected or faulty transceiver drop cable, or the

fact the transceiver does not support this feature (or

the feature is disabled).

In addition to the reporting of network errors, the MAC

engine will also attempt to prevent the creation of any

network error due to the inability of the host to service

the MAC engine. During transmission, if the host fails

to keep the Transmit FIFO filled sufficiently, causing an

underflow, the MAC engine will guarantee the message

is either sent as a runt packet (which will be deleted by

the receiving station) or has an invalid FCS (which will

also cause the receiver to reject the message).

The status of each receive message is available in the

appropriate RMD and CSR areas. FCS and Framing

errors (FRAM) are reported, although the received

frame is still passed to the host. The FRAM error will

only be reported if an FCS error is detected and there

are a non-integral number of bits in the message. The

MAC engine will ignore up to seven additional bits at

the end of a message (dribbling bits), which can occur

under normal network operating conditions. The recep-

tion of eight additional bits will cause the MAC engine

to de-serialize the entire byte, and will result in the

received message and FCS being modified.

The PCnet-ISA II controller can handle up to 7 dribbling

bits when a received packet terminates. During the

reception, the CRC is generated on every serial bit

(including the dribbling bits) coming from the cable,

although the internally saved CRC value is only

updated on the eighth bit (on each byte boundary). The

framing error is reported to the user as follows:

1. If the number of the dribbling bits are 1 to 7 and

there is no CRC error, then there is no Framing error

(FRAM = 0).

2. If the number of the dribbling bits are less than 8

and there is a CRC error, then there is also a

Framing error (FRAM = 1).

3. If the number of dribbling bits = 0, then there is no

Framing error. There may or may not be a CRC

(FCS) error.

Counters are provided to report the Receive Collision

Count and Runt Packet Count used for network statis-

tics and utilization calculations.

Note that if the MAC engine detects a received packet

which has a 00b pattern in the preamble (after the first

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