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T6LE2 Datasheet(PDF) 6 Page - Toshiba Semiconductor |
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T6LE2 Datasheet(HTML) 6 Page - Toshiba Semiconductor |
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6 / 12 page ![]() T6LE2 2006-09-20 6 Device Operation Shift data transfer method Shift Data MODE1 MODE2 Output Mode U/D Pin Input Output Data Transfer Method H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G300 H H 300-out L DO/I DI/O G300 → G299 → G298 → ··· → G1 H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G132 → G170 → ··· → G300 H L 263-out L DO/I DI/O G300 → G299 → G298 → ··· → G170 → G132 →··· → G1 H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G128 → G173 → ··· → G300 L H 256-out L DO/I DI/O G300 → G299 → G298 → ··· → G173 → G128 →··· → G1 L L Don't use The input data (DI/O or DO/I) is latched into the internal register synchronously with the rising edge of the shift clock CPV. At the same time that the data is shifted to the next register at the next rise of CPV, new vertical shift data is latched into. In the output operation, the data in the last shift register (G300 or G1) is output synchronously with the falling edge of CPV. (The output high voltage is the VDD level; the output low voltage is the VSS level.) |
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