ADAR1000ACCZN-R7 datasheet(70/79 Pages) AD

70 / 79 page

Data Sheet

ADAR1000

analog.com

Rev. B | 70 of 79

Table 76. Bit Descriptions for SW_CTRL

Bit

Bit Name

Settings

Description

Reset

Access

SW_DRV_EN_TR

Enables Switch Driver for External Transmit/Receive Switch. 1 = enabled.

0x0

R/W

SW_DRV_EN_POL

Enables Switch Driver for External Polarization Switch. 1 = enabled.

0x0

R/W

TR_SOURCE

Source for Transmit/Receive Control. 0 = TR_SPI, 1 = TR input.

0x0

R/W

TR_SPI

Transmit or Receive mode while in SPI Control. 0 = receive and 1 = transmit.

0x0

R/W

POL

Control for External Polarity Switch Drivers. 0 = outputs 0 V, and 1 = outputs −5 V, if switch is

enabled.

0x0

R/W

Address: 0x032, Reset: 0x00, Name: ADC_CTRL

Table 77. Bit Descriptions for ADC_CTRL

Bit(s)

Bit Name

Settings

Description

Reset

Access

ADC_CLKFREQ_SEL

ADC Clock Frequency Selection. 0 = 2 MHz, 1 = 250 kHz

0x0

R/W

ADC_EN

Turns on ADC and Resets State Machine. 1 = enabled

0x0

R/W

CLK_EN

Turns on Clock Oscillator. 1 = enabled

0x0

R/W

ST_CONV

Active High Triggers Conversion Cycle. Self-clearing

0x0

R/WC

[3:1]

MUX_SEL

ADC Input Signal Select

0x0

R/W

0b000

Temperature Sensor

0b001

Detector 1

0b010

Detector 2

0b011

Detector 3

0b100

Detector 4

ADC_EOC

ADC End of Conversion Signal. Active high; low during conversion.

0x0

Address: 0x033, Reset: 0x00, Name: ADC_OUTPUT

Table 78. Bit Descriptions for ADC_OUTPUT

Bit(s)

Bit Name

Settings

Description

Reset

Access

[7:0]

ADC

ADC Output Word

0x0

Address: 0x034, Reset: 0x00, Name: BIAS_CURRENT_RX_LNA

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