ADAR1000ACCZN-R7 datasheet(13/79 Pages) AD

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Data Sheet

ADAR1000

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. B | 13 of 79

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

Output is set to the CH3_PA_BIAS_OFF value if the PA_ON pin is at logic low. Pin assumes CH3_PA_BIAS_ON

default value upon power up or soft reset.

RF_IO

Common RF Pin for Input in Transmit Mode and Output in Receive Mode. The signal path is ac-coupled via an

on-chip capacitor. The dc bias is 0 V due to the on-chip shunt inductor.

PA_BIAS2

Gate Bias Output for Channel 2 External PA. Output ranges from 0 to −4.8 V, controlled by a combination of

the PA_ON pin, Register 0x02A (CH2_PA_BIAS_ON value), and Register 0x047 (CH2_PA_BIAS_OFF value).

Output is set to the CH2_PA_BIAS_OFF value if the PA_ON pin is at logic low. Pin assumes CH2_PA_BIAS_ON

default value upon power up or soft reset.

A10

PA_BIAS1

Gate Bias Output for Channel 1 External PA. Output ranges from 0 to −4.8 V, controlled by a combination of

the PA_ON pin, Register 0x029 (CH1_PA_BIAS_ON value), and Register 0x046 (CH1_PA_BIAS_OFF value).

Output is set to the CH1_PA_BIAS_OFF value if the PA_ON pin is at logic low. Pin assumes CH1_PA_BIAS_ON

default value upon power up or soft reset.

A11

LNA_BIAS

Gate Bias Output for External LNA. Output ranges from 0 to −4.8 V, controlled by a combination of

(LNA_BIAS_OFF value). Output floats if Register 0x030, Bit 4 is at logic low. Pin is floating upon power up or

after a soft reset.

PA_ON

PA Enable Input. This pin is used when device transmit/receive operation is controlled via the TR pin. This

pin is not used with SPI control. When BIAS_CTRL (Bit 6 in Register 0x30) = 1 and TR_SOURCE (Bit 2 in

EXT_PAx_BIAS_ON registers when the TR pin = 1, and EXT_PAx_BIAS_OFF registers when the TR pin = 0

(where x = 1 to 4). All PA bias voltage outputs assume the corresponding EXT_PAx_BIAS_OFF register values

if the PA_ON pin is at logic low (see Table 16). This pin is internally pulled up to the 1.8 V low dropout (LDO)

regulator bias voltage with a 100 kΩ resistor.

TR_POL

Gate Control Output for External Polarization Switch (0 V or −5 V).

TR_SW_POS

Gate Control Positive Output for External Transmit and Receive Switch (0 V or 3.3 V). Pin is floating upon power

up or after a soft reset.

B11

AVDD1

−5 V Power Supply. AVDD1 provides the negative currents for sinking the PA_BIASx and LNA_BIAS outputs.

If the PA_BIASx and LNA_BIAS pins are not used, the user can connect AVDD1 to ground to reduce power

consumption and to use a single voltage supply. It is recommended to power up the AVDD3 pins (3.3 V) before

or at the same time as the AVDD1 pin (−5 V).

TX3

Channel 3 Output in Transmit Mode. This pin is ac-coupled via an on-chip balun and series capacitor.

C13

RX2

Channel 2 Input in Receive Mode. This pin is ac-coupled via an on-chip balun.

RX3

Channel 3 Input in Receive Mode. This pin is ac-coupled via an on-chip balun.

E13

TX2

Channel 2 Output in Transmit Mode. This pin is ac-coupled via an on-chip balun and a series capacitor.

DET4

Channel 4 Power Detector Input. DET4 is internally ac-coupled and enabled by Register 0x030, Bit 0. The

nominal operating input power range is −20 dBm to +10 dBm. If this pin is unused, it is recommended to leave

the detector disabled and either provide a 50 Ω termination or ground the input.

G13

DET2

Channel 2 Power Detector Input. DET2 is internally ac-coupled and enabled by Register 0x030, Bit 2. The

nominal operating input power range is −20 dBm to +10 dBm. If this pin is unused, it is recommended to leave

the detector disabled and either provide a 50 Ω termination or ground the input.

TX4

Channel 4 Output in Transmit Mode. This pin is ac-coupled via an on-chip balun and a series capacitor.

J13

RX1

Channel 1 Input in Receive Mode. This pin is ac-coupled via an on-chip balun.

RX4

Channel 4 Input in Receive Mode. This pin is ac-coupled via an on-chip balun.

L13

TX1

Channel 1 Output in Transmit Mode. This pin is ac-coupled via an on-chip balun and a series capacitor.

CSB

SPI Chip Select Input (1.8 V CMOS Logic). Serial communication is enabled when CSB goes low. When CSB

goes high, serial data is loaded into the register corresponding to the address in the instruction cycle (see Figure

2) in write mode.

SDO

SPI Serial Data Output (1.8 V CMOS Logic). Enabled when SDO ACTIVE Bit = 1. Used in 4-wire SPI protocol.

Pin has a readback error when sharing a bus with other chips. See SDO Readback Problem and Solution.

SDIO

SPI Serial Data Input and Output (1.8 V CMOS Logic). 4-wire SPI protocol if SDO ACTIVE Bit = 1; 3-wire SPI

protocol when SDO ACTIVE Bit = 0.

SCLK

SPI Serial Clock Input (1.8 V CMOS Logic). In write mode, data is sampled on the rising edge of SCLK. During a

read cycle, output data changes at the falling edge of SCLK.

ADAR1000ACCZN-R7 Datasheet(PDF) 13 Page - Analog Devices

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