PCA2129TSLASHQ900SLASH2 datasheet(25/84 Pages) NXP

25 / 84 page

PCA2129

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 19 December 2014

25 of 84

NXP Semiconductors

PCA2129

Automotive accurate RTC with integrated quartz crystal

Once the override mode is entered, the device is immediately released from the reset

state and the set-up operation can commence.

The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be

logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0

during normal operation has no effect except to prevent accidental entry into the PORO

mode.

8.8 Time and date function

Most of these registers are coded in the Binary Coded Decimal (BCD) format.

8.8.1 Register Seconds

Fig 13. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus

Table 21.

Seconds - seconds and clock integrity register (address 03h) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

OSF

SECONDS (0 to 59)

Reset

value

XXX

Table 22.

Seconds - seconds and clock integrity register (address 03h) bit description

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

Value

Place value Description

OSF

clock integrity is guaranteed

clock integrity is not guaranteed:

oscillator has stopped and chip reset has occurred

since flag was last cleared

6 to 4

SECONDS

0 to 5

ten’s place

actual seconds coded in BCD format

3to0

0 to9

unit place

PCA2129T/Q900/2 Datasheet(PDF) 25 Page - NXP Semiconductors

PCA2129T/Q900/2 Datasheet(HTML) 25 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL