PCA2129TSLASHQ900SLASH2 datasheet(82/84 Pages) NXP

82 / 84 page

PCA2129

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Product data sheet

Rev. 5 — 19 December 2014

82 of 84

NXP Semiconductors

PCA2129

Automotive accurate RTC with integrated quartz crystal

27. Figures

Fig 1.

Block diagram of PCA2129 . . . . . . . . . . . . . . . . . .3

Fig 2.

Pin configuration for PCA2129 (SO16) . . . . . . . . .4

Fig 3.

Position of the stubs from the package assembly

process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 4.

Handling address registers . . . . . . . . . . . . . . . . . .6

Fig 5.

Battery switch-over behavior in standard mode with

bit BIE set logic 1 (enabled) . . . . . . . . . . . . . . . . .18

Fig 6.

Battery switch-over behavior in direct switching

mode with bit BIE set logic 1 (enabled) . . . . . . . .19

Fig 7.

Battery switch-over circuit, simplified block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 8.

Battery low detection behavior with bit BLIE set logic

1 (enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 9.

Typical driving capability of VBBS: (VBBS - VDD) with

respect to the output load current IBBS. . . . . . . . .22

Fig 10. Power failure event due to battery discharge: reset

occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 11. Dependency between POR and oscillator . . . . . .24

Fig 12. Power-On Reset (POR) system. . . . . . . . . . . . . .24

Fig 13. Power-On Reset Override (PORO) sequence, valid

for both I2C-bus and SPI-bus. . . . . . . . . . . . . . . .25

Fig 14. Data flow of the time function. . . . . . . . . . . . . . . .30

Fig 15. Access time for read/write operations . . . . . . . . .31

Fig 16. Alarm function block diagram. . . . . . . . . . . . . . . .32

Fig 17. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .35

Fig 18. WD_CD set logic 1: watchdog activates an interrupt

when timed out . . . . . . . . . . . . . . . . . . . . . . . . . .38

Fig 19. Timestamp detection with two push-buttons on the

TS pin (for example, for tamper detection) . . . . .39

Fig 20. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .45

Fig 21. INT example for SI and MI when TI_TP is logic 146

Fig 22. INT example for SI and MI when TI_TP is logic 046

Fig 23. Example of shortening the INT pulse by clearing the

MSF flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 24. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .48

Fig 25. STOP bit functional diagram . . . . . . . . . . . . . . . .49

Fig 26. STOP bit release timing . . . . . . . . . . . . . . . . . . . .50

Fig 27. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .51

Fig 28. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .51

Fig 29. Data transfer overview . . . . . . . . . . . . . . . . . . . . .52

Fig 30. SPI-bus write example . . . . . . . . . . . . . . . . . . . . .53

Fig 31. SPI-bus read example . . . . . . . . . . . . . . . . . . . . .53

Fig 32. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Fig 33. Definition of START and STOP conditions. . . . . .54

Fig 34. System configuration . . . . . . . . . . . . . . . . . . . . . .55

Fig 35. Acknowledgement on the I2C-bus . . . . . . . . . . . .55

Fig 36. Bus protocol, writing to registers . . . . . . . . . . . . .56

Fig 37. Bus protocol, reading from registers . . . . . . . . . .56

Fig 38. Device diode protection diagram of PCA2129 . . .57

Fig 39. IOL on pin SDA/CE . . . . . . . . . . . . . . . . . . . . . . . .61

Fig 40. IDD as a function of temperature . . . . . . . . . . . . .61

Fig 41. IDD as a function of VDD . . . . . . . . . . . . . . . . . . . .62

Fig 42. Typical IDD as a function of the power management

settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Fig 43. Typical characteristic of frequency with respect to

temperature of PCA2129 . . . . . . . . . . . . . . . . . . .64

Fig 44. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Fig 45. I2C-bus timing diagram; rise and fall times refer to

30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Fig 46. General application diagram . . . . . . . . . . . . . . . . 69

Fig 47. Package outline SOT162-1 (SO16)

of PCA2129T. . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Fig 48. Footprint information for reflow soldering of

SOT162-1 (SO16) of PCA2129T . . . . . . . . . . . . 72

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