DSP56720 datasheet(46/54 Pages) FREESCALE

Part #	DSP56720

Description	SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors

PDF	54 Pages

Scroll/Zoom	100%

Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

Logo

46 / 54 page

SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4)

Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

Tclk

–

Input setup to LCLK (except LGTA/LUPWAIT)

Tin_s

8–

Input hold from LCLK (except LGTA/LUPWAIT)1

Tin_h

-1

–

LGTA valid time

Tgta

–

LUPWAIT valid time

Tupwait

–

LALE negedge to LAD (address phase) invalid (address

latch hold time)

Tale_h

5–

LALE valid time

Tale

–

Output setup from LCLK (except LAD[23:0] and LALE)

Tout_s

–

Output hold from LCLK (except LAD[23:0] and LALE)

Tout_h

–

Tin_s

Tin_h

LGTA

asynchronous input

LA[2:0]/LBCTL/LCS[7:0]

LOE/LWE

LCKE/LSDA10/LSDDQM

LGPL[5:0]

Output Signals

LCLK

LAD[23:0] (data)

Tclk

LUPWAIT

asynchronous input

Tgta

Tupwait

Tout_s

Tout_h

LALE

Tad_s

Tad_h

LAD[23:0]

Tad_z

LSDWE/LSDRAS/LSDCAS

Tale

Tale_h

DSP56720 Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

DSP56720 Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL