DSP56720 datasheet(17/54 Pages) FREESCALE

17 / 54 page

SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1

Freescale Semiconductor

Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered)

Figure 14. MODE Select Set-Up and Hold Timing Diagram

2.2

Module-Level Specifications

For a summary of the module-level specifications in this section, see Table 10.

Table 10. Module-Level Specifications

For

See

Section 2.2.1, “Serial Host Interface (SHI) SPI Protocol Timing”

on page 18

Section 2.2.2, “Serial Host Interface (SHI) I2C Protocol Timing”

on page 24

Section 2.2.3, “Programming the SHI I2C Serial Clock”

on page 26

Section 2.2.4, “Enhanced Serial Audio Interface (ESAI) Timing”

on page 27

Section 2.2.5, “Timer Timing”

on page 32

Section 2.2.6, “GPIO Timing”

on page 32

Section 2.2.7, “JTAG Timing”

on page 33

Section 2.2.8, “Watchdog Timer Timing”

on page 35

Section 2.2.9, “Host Data Interface (HDI24) Timing”

on page 35

Section 2.2.10, “S/PDIF Timing”

on page 42

Section 2.2.11, “EMC Timing (DSP56720 only)”

on page 43

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

RESET

MODA, MODB,

MODC, MODD,

PINIT

VIH

IRQA, IRQB,

IRQC,IRQD, NMI

VIH

VIL

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