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DAC1221 Datasheet(PDF) 12 Page - Texas Instruments |
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DAC1221 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 17 page  12 ® DAC1221 SYMBOL DESCRIPTION MIN NOM MAX UNITS fXIN XIN Clock Frequency 1 2.5 MHz tXIN XIN Clock Period 400 1000 ns t1 XIN Clock High 0.4 • tXIN ns t2 XIN Clock LOW 0.4 • tXIN ns t3 SCLK HIGH 5 • tXIN ns t4 SCLK LOW 5 • tXIN ns t5 Data In Valid to SCLK Falling Edge (Setup) 40 ns t6 SCLK Falling Edge to Data In Not Valid (Hold) 20 ns t7 Data Out Valid After Rising Edge of SCLK (Hold) 0 ns t8 SCLK Rising Edge to New Data Out Valid (Delay)(1) 50 ns t9 Falling Edge of Last SCLK for INSR to Rising Edge of First 13 • tXIN ns SCLK for Register Data ns t10 Falling Edge of CS to Rising Edge of SCLK 11 • tXIN ns t11 Falling Edge of Last SCLK for INSR to SDIO as Output 8 • tXIN 10 • tXIN ns t12 SDIO as Output to Rising Edge of First SCLK for Register Data 4 • tXIN ns t13 Falling Edge of Last SCLK for Register Data to SDIO Tri-State 4 • tXIN 6 • tXIN ns t14 Falling Edge of Last SCLK for Register Data to Rising Edge 41 • tXIN ns of First SCLK of next INSR (CS Tied LOW) t15 Rising Edge of CS to Falling Edge of CS (Using CS) 22 • tXIN ns NOTE: (1) With 10pF load. TABLE VIII. Digital Timing Characteristics. t XIN t 1 X IN t 2 t 3 t 4 t 5 t 7 t 6 t 8 SCLK SDIO t 14 t 9 IN7 IN0 IN1 INM IN1 IN0 IN7 Write Register Data IN7 OUT0 OUT1 OUTM IN1 IN0 IN7 Read Register Data SCLK SDIO SDIO CS SCLK SDIO t 15 t 10 IN7 IN0 IN1 IN0 IN1 IN7 INM t 10 t 9 Write Register Data SDIO IN7 OUT0 OUT1 IN0 IN1 IN7 OUTM Read Register Data FIGURE 5. XIN Clock Timing. FIGURE 6. Serial Input/Output Timing. FIGURE 7. Serial Interface Timing (CS always LOW). FIGURE 8. Serial Interface Timing (using CS). |
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