WM8994ECSSLASHR datasheet(178/363 Pages) CIRRUS

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WM8994

178

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R769 (0301h)

AIF1 Control

(2)

AIF1DACL_

SRC

AIF1 Left Receive Data Source Select

0 = Left DAC receives left interface data

1 = Left DAC receives right interface data

AIF1DACR_

SRC

AIF1 Right Receive Data Source Select

0 = Right DAC receives left interface data

1 = Right DAC receives right interface data

11:10

AIF1DAC_B

OOST [1:0]

AIF1 Input Path Boost

00 = 0dB

01 = +6dB (input must not exceed -6dBFS)

10 = +12dB (input must not exceed -12dBFS)

11 = +18dB (input must not exceed -18dBFS)

R774 (0306h)

AIF1 DAC

Data

AIF1DACL_

DAT_INV

AIF1 Left Receive Data Invert

0 = Not inverted

1 = Inverted

AIF1DACR_

DAT_INV

AIF1 Right Receive Data Invert

0 = Not inverted

1 = Inverted

R775 (0307h)

AIF1 ADC

Data

AIF1ADCL_

DAT_INV

AIF1 Left Transmit Data Invert

0 = Not inverted

1 = Inverted

AIF1ADCR_

DAT_INV

AIF1 Right Transmit Data Invert

0 = Not inverted

1 = Inverted

Table 90 AIF1 Digital Audio Data Control

AIF1 - MONO MODE

AIF1 can be configured to operate in mono DSP mode by setting AIF1_MONO = 1 as described in

Table 91. Note that mono mode is only supported in DSP mode, ie when AIF1_FMT = 11.

In mono mode, the Left channel data or the Right channel data may be selected for output on

ADCDAT1. The selected channel is determined by the AIF1ADC1L_ENA and AIF1ADC1R_ENA bits.

(If both bits are set, then the Right channel data is selected.)

In mono mode, the DACDAT1 input can be enabled on the Left and/or Right signal paths using the

AIF1DAC1L_ENA and AIF1DAC1R_ENA bits. The mono input can be enabled on both paths at the

same time if required.

In mono mode, the number of BCLK cycles per LRCLK frame must be less than double the AIF1 word

length. This requires AIF1DAC_RATE to be less than double the value selected by the AIF1_WL

than double the value selected by the AIF1_WL register. See Table 89 for details of the

AIF1DAC_RATE and AIF1ADC_RATE registers.

Note that AIF1 TDM mode and AIF1 Mono mode cannot be supported simultaneously.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R769 (0301h)

AIF1 Control

(2)

AIF1_MONO

AIF1 DSP Mono Mode

0 = Disabled

1 = Enabled

Note that Mono Mode is only supported when

AIF1_FMT = 11. The number of BCLK cycles

per LRCLK frame must be less the 2 x AIF1

Word Length.

Table 91 AIF1 Mono Mode Control

WM8994ECS/R Datasheet(PDF) 178 Page - Cirrus Logic

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