4

A

1

2

3

D

C

B

OUTRB

PGND

OUTLA

AGND

OUTRA

INR+

INR-

INL-

INL+

G1

G0

PVDD

SDL

SDR

AVDD

OUTLB

LM48411

www.ti.com

SNAS399G – SEPTEMBER 2007 – REVISED MAY 2013

Connection Diagram

Figure 3. DSBGA - Top View

See YZR0016 Package

PIN DESCRIPTIONS

Bump

Name

Function

A1

OUTLB

Left Channel output B

A2

SDL

Left channel active low shutdown

A3

PGND

Power GND

A4

OUTRB

Right channel output B

B1

OUTLA

Left channel output A

B2

SDR

Right channel active low shutdown

B3

AGND

Ground

B4

OUTRA

Right channel output A

C1

PVDD

Power VDD

C2

G1

Gain setting input 1

C3

G0

Gain setting input 0

C4

AVDD

Power supply

D1

INL+

Non-inverting left channel input

D2

INL-

Inverting left channel input

D3

INR-

Inverting right channel input

D4

INR+

Non-inverting right channel input

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2007–2013, Texas Instruments Incorporated

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