R/W

Bit 0

1

Bit 1

1

Bit 2

0

Bit 3

0

Bit 4

0

Bit 5

1

Bit 7

1

Bit 6

MSB

LSB

I

2

C Slave Address (chip address)

start

msb Chip Address lsb

w

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

ack from slave

ack from slave

SCL

SDA

start

Id = 63h

w

ack

addr = 0Ah

ack

ack

Data = 03h

stop

LM3556

SNVS796D – AUGUST 2011 – REVISED OCTOBER 2015

www.ti.com

Programming (continued)

W = Write (SDA = '0')

R = Read (SDA = '1')

Ack = Acknowledge (SDA Pulled Down By Either Master Or Slave)

ID= Chip Address, 63h For LM3556

Figure 31. Write Cycle

7.5.1.4 I2C-Compatible Chip Address

The device address for the LM3556 is 1100011 (63). After the START condition, the I2C-compatible master

sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE and R/W = 1

indicates a READ. The second byte following the device address selects the register address to which the data

will be written. The third byte contains the data for the selected register.

Figure 32. I2C-Compatible Device Address

7.5.1.5 Transferring Data

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte

of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is

generated by the master. The master releases SDA (HIGH) during the 9th clock pulse. The LM3556 pulls down

SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has

been received.

18

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