Output

Control

Power Conditioning

VDD

3

3

FS0

LVPECL

or LVDS

or HCSL

FS1

3

= tri-state

PLL

¥

ROM

(Pin Control)

3

OS

Integrated

Oscillator

XO

N Div

™û fractional

Integer Div

GND

OE

LMK61PD0A2

www.ti.com

SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015

9 Detailed Description

9.1 Overview

The LMK61PD0A2 is a pin selectable oscillator that generates commonly used reference clocks, greater than

100 MHz, with less than 200 fs, rms max random jitter.

9.2 Functional Block Diagram

NOTE

Control blocks are compatible with 1.8/2.5/3.3 V I/O voltage levels.

9.3 Feature Description

9.3.1 Device Block-Level Description

The LMK61PD0A2 comprises of an integrated oscillator that includes a 50 MHz crystal, a fractional PLL with

integrated VCO. Completing the device is the combination of an integer output divider and a universal differential

output buffer. The on-chip ROM contains seven pre-programmed output frequency plans that selects the

appropriate settings for the integrated oscillator, PLL blocks and output divider. Table 1 lists the supported output

frequency plans that can be selected by pin-strapping FS[1:0] as required. Table 2 lists the supported output

types that can be selected by pin-strapping OS and OE as required. The device is powered by on-chip low

dropout (LDO) linear voltage regulators and the regulated supply network is partitioned such that the sensitive

analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs

provide isolation from any noise in the external power supply rail with a PSRR of better than -70 dBc at 50 kHz to

1 MHz ripple frequencies at 3.3 V device supply.

9.3.2 Device Configuration Control

The LMK61PD0A2 selects an output frequency plan and output type using control pins FS[1:0].

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