1

R3 =

+

-

1

1

R1

GT

R2

1

1

R1

VLT

VREF (GT)

R2

-

=

VREF (GT)

VUT1

R1 =

1

1

1

R3

R2

R1

GT =

+

+

VUT = R1 (VREF) GT

VLT = R1 // R2 (VREF) GT

+

-

VB

LM385A-1.2V

LMC7215

R1

R3

R2

R4

VREF

2.74M

180k

768k

301k

2.2PF

VB

4 Cells

NiMH

SHDN

GND

IN

OUT

LP3982

FAULT

100k

2.2PF

CERAMIC

10

LP3982

SNVS185F – FEBRUARY 2002 – REVISED APRIL 2017

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Copyright © 2002–2017, Texas Instruments Incorporated

7.4 Device Functional Modes

7.4.1 Shutdown

The LP3982 goes into sleep mode when the SHDN pin is in a logic low condition. During this condition, the pass

transistor, error amplifier, and bandgap are turned off, reducing the supply current to 1 nA typical. The maximum

voltage for a logic low at the SHDN pin is 0.4 V. A minimum voltage of 2 V at the SHDN pin turns the LP3982

back on. The SHDN pin may be directly tied to VIN to keep the part on. The SHDN pin may exceed VIN but not

the maximum of 6.5 V.

Figure 13 shows an application that uses the SHDN pin. It detects when the battery is too low and disconnects

the load by turning off the regulator. A micropower comparator (LMC7215) and reference (LM385) are combined

with resistors to set the minimum battery voltage. At the minimum battery voltage, the comparator output goes

low and tuns off the LP3982 and corresponding load. Hysteresis is added to the minimum battery threshold to

prevent the battery's recovery voltage from falsely indicating an above minimum condition. When the load is

disconnected from the battery, it automatically increases in terminal voltage because of the reduced IR drop

across its internal resistance. The minimum battery detector of Figure 13 has a low detection threshold (VLT) of

3.6 V that corresponds to the minimum battery voltage. The upper threshold (VUT) is set for 4.6 V to exceed the

recovery voltage of the battery.

Figure 13. Minimum Battery Detector that Disconnects the Load Via the SHDN Pin of the LP3982

Resistor value for VUT and VLT are determined as follows:

(1)

(The application of Figure 13 used a GT of 5 μ mho.)

(2)

(3)

(4)

The above procedure assumes a rail-to-rail output comparator. Essentially, R2 is in parallel with R1 prior to

reaching the lower threshold, then R2 becomes parallel with R3 for the upper threshold. Note that the application

requires rail-to-rail input as well.

The resistor values shown in Figure 13 are the closest practical to calculated values.