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PCM1807PW Datasheet(PDF) 14 Page - Texas Instruments |
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PCM1807PW Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 34 page ![]() www.ti.com SERIAL AUDIO DATA INTERFACE INTERFACE MODE DATA FORMAT PCM1807 SLES147 – SEPTEMBER 2005 The PCM1807 interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9). The PCM1807 supports master mode and slave mode as interface modes, which are selected by MD1 and MD0. MD1 and MD0 are controlled through the serial control port as shown in Table 2. In master mode, the PCM1807 provides the timing of serial audio data communications between the PCM1807 and the digital audio processor or external circuit. While in slave mode, the PCM1807 receives the timing for data transfer from an external controller. Table 2. Interface Modes MD1 MD0 INTERFACE MODE 0 0 Slave mode (256 fS, 384 fS, 512 fS autodetection) (default) 0 1 Master mode (512 fS) 1 0 Master mode (384 fS) 1 1 Master mode (256 fS) Master mode In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1807. The frequency of BCK is fixed at 64 BCK/frame. Slave mode In slave mode, BCK and LRCK work as input pins. The PCM1807 accepts 64 BCK/frame or 48 BCK/frame format (only for a 384 fS system clock), not 32 BCK/frame format. The PCM1807 supports two audio data formats in both master and slave modes. The data formats are selected by FMT, which is controlled through the serial control port as shown in Table 3. Figure 21 illustrates the data formats in slave mode and master mode. Table 3. Data Format FORMAT NO. FMT FORMAT 0 0 I2S, 24-bit (default) 1 1 Left-justified, 24-bit 14 |
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