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SYSTEM CLOCK INPUT

SCKI

0.8 V

SCKI

2 V

tw(SCKL)

tw(SCKH)

T0005B07

POWER-ON AND RESET FUNCTIONS

POWER-DOWN FUNCTION

OVERSAMPLING RATIO

PCM1804

SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007

PRINCIPLES OF OPERATION (continued)

The PCM1804 supports 128 fS, 192 fS (only in master mode at quad rate), 256 fS, 384 fS, 512 fS, and 768 fS as a

system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 18).

Table 3 shows the relationship of typical sampling frequency and the system clock frequency, and Figure 32

shows system clock timing. In master mode, the system clock rate is selected by OSR2 (pin 11), OSR1 (pin 10),

and OSR0 (pin 9) as shown in Table 1. In slave mode, the system clock rate is automatically detected. In DSD

mode, OSR2 (pin 11), OSR1 (pin 10), OSR0 (pin 9), and the system clock frequency are fixed as shown in

Table 1 and Table 3.

PARAMETER

MIN

UNIT

tw(SCKH)

System clock pulse duration, HIGH

11

ns

tw(SCKL)

System clock pulse duration, LOW

11

ns

Figure 32. System Clock Input Timing

The PCM1804 has both an internal power-on-reset circuit and RST (pin 19). For internal power-on reset,

initialization (reset) is performed automatically at the time when the power supply VDD exceeds 2 V (typical) and

VCC exceeds 4 V (typical). RST accepts external forced reset, and a low level on RST initiates the reset

sequence. Because an internal pulldown resistor terminates RST, no connection of RST is equivalent to a

low-level input. Because the system clock is used as a clock signal for the reset circuit, the system clock must be

supplied as soon as power is supplied; more specifically, at least three system clocks are required prior to VDD >

2 V, VCC > 4 V, and RST = high. While VDD < 2 V (typical), VCC < 4 V (typical), or RST = low, and 1/fS (maximum)

count after VDD > 2 V (typical),VCC > 4 V (typical) and RST = high, the PCM1804 stays in the reset state and the

digital output is forced to zero. The digital output is valid after the reset state is released and the time of 1116/fS

has passed. Figure 33 and Figure 34 illustrate the internal power-on-reset and external-reset timing, respectively.

Figure 35 illustrates the digital output for power-on reset and RST control. The PCM1804 needs RST = low when

control pins are changed or in slave mode when SCKI, LRCK, and BCK are changed.

The PCM1804 has a power-down feature that is controlled by RST (pin 19). Entering the power-down mode is

done by keeping the RST input level low for more than 65536/fS. In the master mode, the SCKI (pin 18) is used

as the clock signal for the power-down counter. While in the slave mode, SCKI (pin 18) and LRCK (pin 17) are

used as the clock signal. The clock(s) must be supplied until the power-down sequence completes. As soon as

RST goes high, the PCM1804 starts the reset-release sequence described in the Power-On and Reset Functions

section.

The oversampling ratio is selected by OSR2 (pin 11), OSR1 (pin 10), and OSR0 (pin 9) as shown in Table 1 and

Table 2. The PCM1804 needs RST = low when logic levels on the OSR2, OSR1, and OSR0 pins are changed.

18

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