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PCM1804DB Datasheet(PDF) 28 Page - Texas Instruments |
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PCM1804DB Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 39 page ![]() www.ti.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + C1 + C3 + C5 + − L-Channel In Format [1:0] Master/Slave Oversampling Ratio [2:0] HPF Bypass 3.3 V C2 C4 + + + C6 5 V Control + − R-Channel In Overflow Reset System Clock Data Clock L-Channel Data Out Audio Data Processor PCM1804 R-Channel Data Out S0058-02 VREFL AGNDL VCOML VINL+ VINL− FMT0 FMT1 S/M OSR0 OSR1 OSR2 BYPAS DGND VDD VREFR AGNDR VCOMR VINR+ VINR− AGND VCC OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL DATA/DSDR PCM1804 SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007 Figure 43 illustrates a typical circuit connection diagram in the DSD data format operation. A. C1, C2, C5, and C6: Bypass capacitors, 0.1- μF ceramic and 10-μF tantalum, depending on layout and power supply B. C3 and C4: Bypass capacitors, 0.1- μF tantalum, depending on layout and power supply Figure 43. Typical Circuit Connection Diagram for DSD 28 Submit Documentation Feedback Copyright © 2001–2007, Texas Instruments Incorporated Product Folder Link(s): PCM1804 |
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