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PIN ASSIGNMENTS

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28

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VREFL

AGNDL

VCOML

VINL+

VINL−

FMT0

FMT1

S/M

OSR0

OSR1

OSR2

BYPAS

DGND

VDD

VREFR

AGNDR

VCOMR

VINR+

VINR−

AGND

VCC

OVFL

OVFR

RST

SCKI

LRCK/DSDBCK

BCK/DSDL

DATA/DSDR

PCM1804 PACKAGE

(TOP VIEW)

P0007-02

PCM1804

SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.

These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to

MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than

maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together

or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic

voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication

Electrostatic Discharge (ESD) (SSYA008), available from Texas Instruments.

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Product Folder Link(s): PCM1804