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STM32F205RFT6 Datasheet(PDF) 183 Page - STMicroelectronics

Part # STM32F205RFT6
Description  ARM®-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  184 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F205RFT6 Datasheet(HTML) 183 Page - STMicroelectronics

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DocID15818 Rev 15
183/184
STM32F20xxx
Revision history
183
04-Nov-2013
11
(continued)
Removed Appendix A Application block diagrams.
Updated Figure 77: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat
package outline and Table 87: LQFP64 – 10 x 10 mm 64 pin low-profile
quad flat package mechanical data. Updated Figure 80: LQFP100, 14 x
14 mm 100-pin low-profile quad flat package outline, Figure 83:
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline,
Figure 86: LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm,
package outline. Updated Figure 88: UFBGA176+25 - ultra thin fine
pitch ball grid array 10 × 10 × 0.6 mm, package outline and Figure 88:
UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm,
package outline.
27-Oct-2014
12
Updated VBAT voltage range in Figure 19: Power supply scheme. Added
caution note in Section 6.1.6: Power supply scheme.
Updated VIN in Table 14: General operating conditions.
Removed note 1 in Table 23: Typical and maximum current
consumptions in Stop mode.
Updated Table 45: I/O current injection susceptibility, Section 6.3.16:
I/O port characteristics and Section 6.3.17: NRST pin characteristics.
Removed note 3 in Table 69: Temperature sensor characteristics.
Updated Figure 79: WLCSP64+2 - 0.400 mm pitch wafer level chip size
package outline and Table 88: WLCSP64+2 - 0.400 mm pitch wafer
level chip size package mechanical data. Added Figure 83: LQFP100
marking (package top view) and Figure 86: LQFP144 marking (package
top view).
2-Feb-2016
13
Updated Section 1: Introduction.
Updated Table 32: HSI oscillator characteristics and its footnotes.
Updated Figure 36: PLL output clock waveforms in center spread mode,
Figure 37: PLL output clock waveforms in down spread mode,
Figure 54: Power supply and reference decoupling (VREF+ not
connected to VDDA) and Figure 55: Power supply and reference
decoupling (VREF+ connected to VDDA).
Updated Section 7: Package information and its subsections.
24-Jun-2016
14
Updated figures 1, 2 and 3 in Section 2.1: Full compatibility throughout
the family.
Updated Device marking and Figure 83 in Section 7.3: LQFP100
package information.
Updated Device marking and Figure 86 in Section 7.4: LQFP144
package information.
Updated Section 7.6: UFBGA176+25 package information with
introduction of Device marking and Figure 91.
Updated Table 96: Ordering information scheme.
11-Aug-2016
15
Updated Features, Section 7.2: WLCSP64+2 package information and
title of Section 8: Ordering information.
Updated Figure 54: Power supply and reference decoupling (VREF+
not connected to VDDA).
Table 97. Document revision history (continued)
Date
Revision
Changes



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